1. Field of the Invention
The present invention relates generally to a method and apparatus for design, layout, and processing, and the manufacture of very large area, wafer scale, charge-coupled device (CCD) image sensors and, in particular, to a method and apparatus for improving the manufacturing yield of wafer scale CCD sensors by providing a layout structure which is tolerant to defects bridging between strapping bus lines and defects in polysilicon gate bus lines.
2. Description of Related Art
Charge-coupled device image sensors are fabricated using techniques generally described as large scale integrated (LSI) circuit, very large scale integrated (VLSI) circuit, ultra-large scale integrated (ULSI) circuit, and now wafer scale integrated (WSI) circuit silicon processing. The processing involves application of multiple layers of silicon dioxide, silicon nitride, polysilicon, ion implant, diffusion, and metal layers, each of which is photolithographically patterned to produce silicon integrated circuit devices generally known in the art as metal-oxide-silicon (MOS) devices. Integrated circuits are also fabricated using bi-polar, gallium arsenide (GaAs), and other technologies. The charge-coupled device (CCD) image sensor is fabricated using variations of typical MOS device processing techniques.
During the fabrication of CCD image sensors (as well as all MOS, bi-polar, etc. devices), particulate contamination occurs which manifests itself as deposited or printed artifacts in one or more of the patterned layers. The artifacts are randomly dispersed about the surface area of a substrate. The substrate is a slice of single crystal silicon or other semiconductor material which is generally produced with diameters of four, five, six, or eight inches.
Particulate contamination occurring in the course of processing silicon integrated circuits has a finite density and usually a random distribution about the wafer surface. Particulate contamination occurring during masking steps in the process has a high probability of creating undesired features which bridge a gap between two electrically unrelated conductive layers, creating an electrical short and thus a device failure.
Silicon integrated circuits are generally small in area compared with the area of the substrate. Thus, a multiplicity of devices can be fabricated on a single substrate. The randomly distributed masking defects then impact the device yield of any wafer, being manifested as a percentage of the total surviving devices divided by the total potential devices present on the wafer. The resultant yield generally follows exponential or square law relationships based on the area of the device and the defect density produced during the processing. Clearly, with a predetermined defect density, large area devices will suffer substantially larger yield loss per wafer than will be suffered by smaller area devices.
Many techniques are used in silicon integrated circuit processing to minimize gross shorting yield loss on processed silicon wafers. Generally, the techniques employed concentrate on the reduction of contaminants in the silicon fabrication facility. Reduction of contaminants is accomplished by various means, including filtering and purifying the recirculated laboratory air, filtering processing materials such as photoresists, eliminating human contamination in the laboratory, eliminating dust-generating equipment from the laboratory, etc. Such techniques can reduce contamination-induced defect densities to less than one defect per square inch. In general, for silicon devices with small areas (A.ltoreq.0.05 square inches), a defect density of less than 1 defect per square inch will generate a device yield at the wafer level of greater than 85%, which is often acceptable.
Since the defect density in a given silicon wafer processing facility is generally a given quantity, larger area devices (A.gtoreq.0.3 square inches) must be designed to reduce the impact of processing defects on yield or suffer high yield loss, resulting in high manufacturing costs. One technique used in circuit layout is to provide redundant circuit elements in the device design which are idle if the device has no defects, but which can be activated through electrical means to bypass a defective circuit element.
Special process steps may also be employed to reduce the impact of defects on the circuit. Process layers, such as polysilicon, metal, contact, etc., may be redundantly patterned to eliminate defects created by a single patterning of that layer. This is effective since randomly (not systematically) dispersed contamination induced defects have a nearly zero probability of being replicated in successive masking steps.
The design of CCD image sensors requires using dense arrays of repeated imaging cells (pixels) with interconnect structures. Such sensors do not allow for circuit redundancy. Additionally, since a CCD image sensor is used as the photosensing element in a fixed format camera system, no active area can be idle or redundant without reducing the performance of the imaging system. Hence, the entire active area of a CCD sensor must be free of defects of the kind that causes shorting failures.
Masking redundancy has been employed successfully in the manufacture of CCD image sensors at a cost of additional processing steps. This technique is limited to layers which have features large enough or with large enough spacing that the application of a second or redundant mask will not ruin the function of the earlier patterned layer. Mask alignment and photoresist dimensional tolerances, as well as etch process tolerances, limit the practice of mask redundancies to lower density device structures. Masking redundancies will not eliminate all forms of defects (e.g., defects causing bridging or shorting of two conductive layers). One example of defects which cannot be eliminated with redundant masking is the occurrence of tall or very thick features which cannot be properly patterned or etched using conventional photolithographic techniques.
For wafer scale CCD sensor designs with dense polysilicon, contact, and metal patterns, the problem of preventing a known process-induced defect density from causing shorting failures cannot be solved with either circuit redundancy or simple mask redundancies. An attempt to fabricate a single, large area, metal strapped, CCD image sensor on one silicon wafer (e.g., 4-inch diameter) by conventional methods will often produce zero yield.
This invention solves the problem enabling a finite yield of short free CCD sensors with a device area comprising more than 85% of the silicon wafer surface, while the measured gross defect density for the process is large compared to that which, without this invention, would be required to predict a finite short free yield. This invention reduces the probability that known defects, resulting from the silicon processing, will cause a fatal short.
In FIGS. 1A and 1B, CCD image sensor pixels of the full frame type are constructed of three polysilicon layers 10 (designated poly 1, poly 2, and poly 3) patterned in repeated contiguous stripes across a lateral dimension of the array. It should be noted that other forms of CCD image sensors, such as interline transfer, frame transfer, and TDI (time delay and integration), may similarly be constructed of multiple layers of patterned polysilicon layers. The polysilicon stripes or buses are commonly used to supply voltages in a clocked square wave pattern to create potential wells and barriers in bulk silicon channels defined by oxide or implanted channel stops. Photogenerated electrons are collected in integration wells and the packets of charge collected therein are transferred by the clocked square wave patterned voltages into a parallel-to-serial register where the charge is transferred to an output device.
In many applications of CCD image sensors that require large imaging focal plane areas or high speed frame transfer or high speed dithering of the potential wells, the resistance of the polysilicon buses must be lowered to reduce waveform propagation delays due to the large capacitances associated with CCD gate structures. A method for reducing the resistivity of the polysilicon bus lines is to pattern metal bus lines 11 in a network transverse to the polysilicon bus lines and contacting each polysilicon bus line to its corresponding metal bus line through via contacts at close intervals 12. The resultant polysilicon bus segments are low in resistance, and the entire array is said to be "metal strapped" or "metal shunted." The metal straps are positioned such that they run the length of the CCD column along a channel stop and comprise as small a fraction of the pixel as possible. Metal coverage in the pixel results in light reflected from the sensor surface and loss of fill factor. Hence the metal coverage is minimized.
In a known implementation of the metal strapping technique, the metal buses are spaced at intervals equaling the pixel pitch (e.g., 12 microns), and the contacts to the polysilicon layers occur at the pixel frequency. Each metal bus is electrically distinct from its neighbor. It is necessary to have metal bus patterns at every channel stop in the array to ensure equal responsivity from each pixel and avoid photoresponse non-uniformities in the array.
Since the metal pattern is an array of closely spaced, electrically distinct conductors, any pattern defects generated during silicon processing, resulting in a metal bridge between metal buses, causes an electrical short between clock phases and ruins the device.
Silicon wafer processing typically generates several masking related defects per square inch. These defects result from numerous sources, including particulate contaminants in the photoresist, contaminants on the wafer surface, contaminants in the deposited materials, handling damage, etc. The sources of masking defects causing fatal shorting failures have been found to be randomly distributed over the surface area of the wafer with only a slight increase in probability at the wafer edges. FIG. 2 illustrates an exemplary wafer scale CCD full frame image sensor comprising &gt;85% of the usable wafer surface (100 mm diagonal wafer). Masking defects 20 are depicted randomly distributed and of a diameter greater than the array pitch (e.g., 12 microns). Masking defects 20 account for nearly all of the fatal shorting defects in the exemplary sensor.
In such a structure of closely spaced metal bus patterns, a defect large enough to span an pixel (e.g., 12 microns) has a 100% probability of creating a short between the otherwise electrically distinct bus lines.
In FIG. 3, several different types of short-causing defects are illustrated. Metal bridging defects 30 comprise excess metal shorting between adjacent metal straps. Defect type 30 constitutes the cause of about 50% of the fatal CCD defects. Other conductive contaminants 31 may also cause shorting between adjacent metal straps. Voids 32 in the insulating oxide layer between the metal and the underlying polysilicon layers may coincide with multiple polysilicon bus lines causing a metal strap to erroneously contact two or more polysilicon bus lines. Defect types 31 and 32 constitute the causes of about 10% of the fatal CCD defects. Large defects in the polysilicon layer may be contacted through multiple metal via contacts from electrically distinct bus metal layers 33. Defect type 33 constitutes the cause of about 30% of the fatal CCD defects. The remaining 10% of the fatal CCD defects are caused by other more obscure factors.
It is conventionally accepted that these and other forms of contaminant-induced masking defects cannot be eliminated from the typical CCD, MOS, CMOS, bi-polar, etc. fabrication processes. For devices with small active areas, the typical masking defect densities result in a reduction in the net yield of functional devices per fabricated wafer. In the case of the wafer scale CCD sensor, normal defect densities result in zero yield since there is only one device per wafer.
FIG. 4 illustrates a calculated curve fit for the yield of the exemplary wafer scale CCD sensor. The curve 40 indicates that there is an exponential relationship to the yield of Y=e.sup.-AD, where D is the defect density in defects per square inch, and A is the area of the sensor in square inches. The defect density for an exemplary device is 1.3 defects per square inch. The yield for a wafer scale device with an area of about 2 square inches for that defect density is &lt;0.06%. This is manifested by the fact that each bridging defect has a 100% probability of causing a fatal short in this structure. The present invention reduces the probability that a fatal short will result from a bridging defect.